74266 DATASHEET PDF

SN74LS (ACTIVE) Quad 2-input exclusive-NOR gates with open collector outputs. Datasheet ( KB). Description click to collapse contents. The ‘LS is . services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all. Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage High Output Current Low Parameter Min Typ Max Unit.

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This article needs additional citations for verification. From Wikipedia, the free encyclopedia. However, extending the concept of the binary logical operation to three inputs, the SN74S with two shared “C” and four independent “A” and “B” inputs for its four outputs, was a device that followed the truth table:.

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By using this site, you agree to the Terms of Use and Privacy Policy. From Wikipedia, the free encyclopedia.

This page was last edited on 24 Octoberat The two-input version implements logical equalitybehaving according to the truth table to the right, and hence the gate is sometimes called an “equivalence gate”. Please help improve this article by adding citations to reliable sources.

74LS Datasheet(PDF) – Fairchild Semiconductor

Views Read Edit View history. Retrieved 6 May The two-input version implements logical equalitybehaving according to the truth table to the right, and hence the gate is sometimes called an “equivalence gate”.

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December Learn how and when to remove this template message. A 4-bit binary comparator such as the 74LS85 would be one way to achieve a true multi-bit equivalence function. It does not implement a logical “equivalence” function, unlike two-input Exclusive OR gates; for example its output is L ow when all inputs are L ow. If one but not both inputs are high 1a low output 0 results.

In datashert projects Wikimedia Commons. Articles needing additional references from December All articles needing additional references Commons category link is on Wikidata. Both include four independent, two-input, XNOR gates. By using this datashet, you agree to the Terms of Use and Privacy Policy. This article needs additional citations for verification. For the NAND constructions, the lower arrangement offers the advantage of a shorter propagation delay the time delay between an input changing and the output changing.

December Learn how and when to remove this template message.

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Datasheets are readily available in most datasheet databases and suppliers. This page was last edited on 24 Octoberat A high output 1 results if both of the inputs to the gate are the same.

It does not implement a logical “equivalence” function, unlike two-input Exclusive OR gates; for example its output is L ow when all inputs are L ow.

A high output 1 results if both of the inputs to the gate are the same. Views Read Edit View history. A 4-bit binary comparator such as the 74LS85 would be one way to achieve a true multi-bit equivalence datashret.

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XNOR gate circuit using three mixed gates. Unsourced material may be challenged and removed.

However, extending the concept of the binary logical operation to three inputs, the SN74S with two shared “C” and four independent “A” and “B” inputs for its four outputs, was a device that followed the truth table:. Articles needing additional references from December All articles needing additional references Commons category link is on Wikidata.

Retrieved from ” https: For the NOR constructions, the upper arrangement requires fewer gates. Datasheets are readily available in most datasheet databases and suppliers.

For the NOR constructions, the upper arrangement requires fewer gates. There are two symbols for XNOR gates: Unsourced material may be challenged and removed. Retrieved from ” https: Retrieved 6 May There are two symbols for XNOR gates: Both include four independent, two-input, XNOR gates. If one but not both inputs are high 1a low output 0 results.

In other projects Wikimedia Commons. For the NAND constructions, the lower arrangement offers the advantage of a shorter propagation delay the time delay between an input changing and the output changing.